The present invention relates to power management, more particularly to a technique for enabling the power management by lowering the frequency of a video clock (Vclk). The Vclk is a timing signal for displaying on a display device, and includes, for example, a timing signal for outputting display data to an LCD (liquid crystal display) for each pixel.
A technique that is currently employed to reduce the power consumed by electronic circuits involves lowering the frequency of a clock, or halting the clock. Since in recent practice there has been an increase in the power consumed by a CPU (central processing unit), the clock frequency is lowered, or halted, in accordance with the amount of processing required for the CPU. The frequency of a video clock, as it is related to a display device such as an LCD, tends to increase with the resolution and the number of display colors, and accordingly, this causes an increase in the power consumption. However, since lowering the frequency of the video clock causes flickers and deterioration of display quality, it is not employed in normal display devices.
Techniques that are employed to lower the frequency of the video clock, or to reduce the refresh rate of the display device are given hereinafter. It should be noted that reducing the refresh rate is not equivalent to lowering the frequency of the Vclk. The refresh rate can be reduced by extending the horizontal or vertical blanking interval while maintaining the Vclk frequency, or by lowering the Vclk frequency, which is the clock frequency on which all the clocks associated with the display are based, without altering the number of clocks used during a horizontal/vertical blanking interval. Lowering the frequency of the Vclk is an effective means to reduce the power consumption, however, in the present invention, it is used to reduce the refresh rate.
U.S. Pat. No. 5,524,249 discloses a technique for halting. When the supply of power to a display device is halted, a Pclk (substantially the same as a video clock) provides for the lowering the frequency of an Mclk (memory clock: a drive frequency of a video controller) when the supply of the power to a display device is halted in such a suspended state or a standby state. However, there is no description about the manner that the Pclk is lowered or halted during the normal state other than the power saving mode, such as the suspended state or the standby state, and that the Pclk and Mclk are simultaneously lowered in the normal state.
U.S. Pat. No. 5,615,376 discloses a technique for halting a VCLK (video clock) during the horizontal and vertical blanking intervals and for lowering an MCLK when there is no access to the frame buffer. However, no description is given for a technique for lowering the VCLK during a normal display period, and for simultaneously lowering the VCLK and the MCLK in the normal state.
Japanese Unexamined Patent Publication No. Hei 7-64665 discloses a technique for slowing the display timing for an LCD when no data has been written to a display memory for a predetermined period of time and the stored contents have not been changed, if a power voltage drop has been detected, or if the system has fallen into the sleep state. However, no description is given for countermeasures to be taken when flickers occur due to slowing the display timing, and for a technique to be employed to slow the display timing without affecting the display contents.
Japanese Unexamined Patent Publication No. Hei 7-239463 discloses that in an active matrix display device, a refresh operation is performed for several lines (for example, every fourth line in the total of 20 lines) within one frame on the display device, then several frames (four frames, in the above example) are required to refresh the entire screen. In this technique, the above refresh operation is performed as a countermeasure for flickers; however, the effect provided by the operation is inadequate or not satisfactory. In addition, to perform the operation, a circuit provided for a panel must be altered.
Japanese Unexamined Patent Publication No. Hei 6-342148 discloses that in a ferro-electrical liquid crystal display device, only scanning lines in which image data have been altered are refreshed, so that motion picture display such as cursor movement, smooth scrolling, and multi-window, and animated video displays can essentially be performed at high speeds even at the low frame frequency. These operations employ characteristics inherent to the ferro-electrical liquid crystal display device.
Japanese Unexamined Patent Publication No. Hei 9-5789 discloses a technique for lowering the drive frequency of a liquid crystal display device that can rewrite a single pixel arbitrary in the entire pixels. The drive frequency is selected by using a display color, or a motion or a still picture. In addition, it discloses a technique whereby, regardless of whether a still picture or a motion picture is used, the drive frequency is changed in accordance with how much the image to be displayed causes flickers, so that the power consumption is optimized for each display image. The luminance and the display color are also taken into account. However, a special liquid crystal display device that can rewrite a single arbitrary pixel is required.
Japanese Unexamined Patent Publication No. Hei 8-179269 discloses a technique whereby, in order to prevent the occurrence of flicker, data for a positive display having a bright background color and data for a negative display having a dark background color are separately extracted from display data, and the frame frequency of the positive display is raised, while that of the negative display is lowered. However, according to this technique, only two display types, positive and negative, can be identified, and there is no detailed explanation of when the frame frequency should be changed or what method can be used to change it.
Therefore, the problems identified and addressed by the present invention provide for objectives, which include the goals of changing the frequency of a video clock without affecting a display quality. It is yet another objective of the present invention to lower more so the power consumption.
According to a first aspect of the present invention, a method for lowering a frequency of a video clock, includes the steps of detecting an opportunity which causes a reduction of the frequency of the video clock; lowering the frequency of the video clock in a frequency range within which a circuit employing the video clock (a PLL (phase lock loop) circuit in the embodiment) can follow a change in the frequency; and iterating the step of lowering the frequency of the video clock until a predetermined frequency is attained. As a result, a disarrangement of the display contents due to the disruption of the operation of the PLL circuit and etc. can be prevented.
According to another aspect of the present invention, a method for lowering a frequency of a video clock includes, the steps of detecting an opportunity which causes the reduction of the frequency of the video clock; lowering the frequency of the video clock to a predetermined frequency during a vertical blanking interval of a display device that employs the video clock; and maintaining the predetermined frequency of the video clock until change of the frequency is required. Even for a portable computer that employs an LCD display device, the vertical blanking intervals exist just in case the computer is connected to a CRT. Since no display operation is performed during these intervals, by changing the frequency of the video clock during these intervals power saving can be performed without the display contents being disarranged.
According to a third aspect of the present invention, a method for lowering a frequency of a video clock, includes the steps of detecting an opportunity which causes the reduction of the frequency of the video clock; changing a display color on a screen of a display device to a color for which a flicker is not outstanding; and lowering the frequency of the video clock. Conventionally, a technique for changing a drive frequency based on the display color has been disclosed (Japanese Unexamined Patent Publication No. Hei 9-5789), but according to this technique, the frequency of the video clock is never lowered. That is, in the environment provided by Windows 95 (Trademark of Microsoft Corp.) many display colors are employed for which the flicker will become outstanding when the frequency of the video clock is lowered, so that no power will be saved when the method which is based on the display colors is employed. Therefore, to achieve the low power consumption, before lowering the frequency of the video clock, the colors of a display screen are changed to colors for which the flicker is not outstanding. This method is particularly effective for a portable computer when the remaining battery power becomes low while a relatively static application, such as a word processing program, is being executed.
An opportunity which causes the reduction of the frequency of the video clock can be detected in accordance with the type of application whose window is displayed on a screen of a display device. For example, the opportunity is a case where an application is being executed for which the display contents are not frequently changed, and the window of that application is in the foreground and no window is being displayed for another application whose display contents are frequently changed.
The opportunity which causes the reduction of the frequency of the video clock can be a change in the size of a window displayed on the screen of the display device. If, for example, the window of an application whose display contents are frequently changed is minimized, the frequency of the video clock can be lowered.
Furthermore, the opportunity which causes the reduction of the frequency of the video clock can be a change of an operation frequency of an input device by a user. If, for example, there is frequent manipulation of a mouse or a keyboard by a user, the movement of the mouse cursor, etc., should not cause the stress imposed on the user, and the frequency of the video clock should not be lowered at such a time. However, if the frequency at which data is input using the mouse or the keyboard is at or below a predetermined level, the frequency of the video clock may then be lowered.
In addition, the opportunity which causes the reduction of the frequency of the video clock can be a change of the processing contents of a processor. Normally, if the number of commands executed by the processor is reduced, the degree of alteration of the display screen is also reduced. When this change is detected, the frequency of the video clock can be lowered.
A drive frequency of a video controller can be lowered together with the frequency of the video clock. With some disclosed conventional techniques, lowering the frequency of the Mclk occur at the same time as the video clock is halted; however, this never occurs during a normal display operation. In other words, the conventional technique does not teach lowering the drive frequency of the video controller during a normal display period, which is the main feature of the present invention.
The steps of the processing performed in the present invention have been explained. The present invention can also be implemented by a program or a circuit designed to perform these steps, or by a combination of the two. The program which implements the present invention can be stored on a storage medium such as a CD-ROM or a floppy disk, or in a ROM or etc.